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| m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers description these are single-chip microcomputers designed with high-perfor- mance cmos silicon gate technology, including the internal flash memory. these microcomputers support the 7900 series instruction set, which are enhanced and expanded instruction set and are up- per-compatible with the 7700/7751 series instruction set. the cpu of these microcomputers is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. also, the bus interface unit of these microcomputers enhances the memory access efficiency to execute instructions fast. therefore, these mi- crocomputers are suitable for office, business, and industrial equip- ment controller that require high-speed processing of large data. for the internal flash memory, single-power-supply programming and erasure, using a prom programmer or the control by the cen- tral processing unit (cpu), is supported. also, each of these micro- computers has the memory area dedicated for storing a certain software which controls programming and erasure (reprogramming control software). therefore, on these microcomputers, the program can easily be changed even after they are mounted on the board. distinctive features m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 2 m37902fxmhp pin configuration (top view) outline 100p6q-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p6 4 /int 2 ? p6 3 /int 1 ? p6 2 /int 0 ? p6 1 /ta4 in ? p6 0 /ta4 out ? p5 5 /ta2 in /rtp1 1 /ki 1 ? p5 4 /ta2 out /rtp1 0 /ki 0 ? p5 3 /ta1 in /rtp0 3 ? p5 2 /ta1 out /rtp0 2 ? p5 1 /ta0 in /rtp0 1 ? p5 0 /ta0 out /rtp0 0 ? p4 7 /cs 3 ? p4 6 /cs 2 ? p4 5 /cs 1 ? p4 4 /cs 0 ? p4 3 /hold ? p4 0 /ale ? 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p4 2 /hlda ? p4 1 / 1 ? p6 5 /tb0 in ? p6 6 /tb1 in ? p6 7 /tb2 in ? p7 0 /an 0 ? ? p3 0 /rdy ? p3 1 /rd ? p3 2 /blw ? p3 3 /bhw byte v cont reset md0 v ss ? p2 5 /d 13 ? p2 4 /d 12 ? p2 6 /d 14 x in x out v cc ? p2 7 /d 15 ? p2 3 /d 11 ? p2 2 /d 10 ? p2 1 /d 9 ? p2 0 /d 8 ? p1 7 /d 7 /la 7 ? p1 6 /d 6 /la 6 ? p1 5 /d 5 /la 5 ? p1 0 /d 0 /la 0 ? p1 1 /d 1 /la 1 ? p1 2 /d 2 /la 2 v ss ? p10 5 /a 5 ? p10 4 /a 4 ? p10 7 /a 7 ? p10 6 /a 6 ? p11 0 /a 8 ? p11 2 /a 10 ? p11 1 /a 9 ? p11 3 /a 11 ? p11 5 /a 13 ? p11 4 /a 12 ? p11 6 /a 14 ? p0 0 /a 16 ? p11 7 /a 15 ? p0 1 /a 17 ? p0 2 /a 18 ? p0 4 /a 20 ? p0 3 /a 19 ? p0 5 /a 21 ? p0 7 /a 23 md1 ? p0 6 /a 22 ? p1 4 /d 4 /la 4 ? p1 3 /d 3 /la 3 p10 0 /a 0 ? p8 7 /t x d 1 ? p8 6 /r x d 1 ? p8 5 /cts 1 /clk 1 ? p8 4 /cts 1 /rts 1 /int 4 ? p8 3 /t x d 0 ? p10 3 /a 3 ? p10 2 /a 2 ? p10 1 /a 1 ? p8 2 /r x d 0 ? v cc av cc v ref av ss v ss p7 7 /an 7 /ad trg /da 1 /(int 2 ) ? p7 6 /an 6 /da 0 ? p7 5 /an 5 /(int 4 ) ? p7 4 /an 4 /(int 3 ) ? p7 3 /an 3 ? p7 2 /an 2 ? p7 1 /an 1 ? p8 0 /cts 0 /rts 0 /da 2 /int 3 ? nmi p8 1 /cts 0 /clk 0 ? m37902fcmhp m37902fgmhp p5 7 /ta3 in /rtp1 3 /ki 3 ? p5 6 /ta3 out /rtp1 2 /ki 2 ? 3 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers block diagram data bank register dt (8) program counter pc (16) incrementer/decrementer (24) program bank register pg (8) input buffer register ib (16) direct page register dpr0 (16) stack pointer s (16) index register y (16) index register x (16) arithmetic logic unit (16) accumulator b (16) accumulator a (16) instruction register (8) central processing unit (cpu) incrementer (24) program address register pa (24) data address register da (24) bus interface unit (biu) reset md1 reference voltage input v ref (0v) av ss avcc vcc external data bus width select input byte clock generating circuit clock input x in v cont x out data buffer dq 0 (8) instruction queue buffer q 0 (8) data bus (odd) address bus a-d converter (10) uart1 (9) uart0 (9) watchdog timer timer tb1 (16) timer tb2 (16) timer tb0 (16) d-a 1 converter (8) d-a 2 converter (8) timer ta1 (16) timer ta2 (16) timer ta3 (16) timer ta4 (16) timer ta0 (16) ram (note) p8(8) input/output port p8 p7(8) input/output port p7 input/output port p4 p4(8) p10(8) input/output port p10 p6(8) input/output port p6 p5(8) input/output port p5 p11(8) input/output port p11 p1(8) input/output port p1 p2(8) input/output port p2 p3(4) input/output port p3 p0(8) input/output port p0 md0 (0v) vss processor status register ps (11) nmi flash memory (note) d-a 0 converter (8) data bus (even) data buffer dq 1 (8) data buffer dq 2 (8) data buffer dq 3 (8) instruction queue buffer q 1 (8) instruction queue buffer q 2 (8) instruction queue buffer q 3 (8) instruction queue buffer q 4 (8) instruction queue buffer q 5 (8) instruction queue buffer q 6 (8) instruction queue buffer q 7 (8) instruction queue buffer q 8 (8) instruction queue buffer q 9 (8) direct page register dpr1 (16) direct page register dpr2 (16) direct page register dpr3 (16) clock output reset input note: flash memory ram m37902fcmhp 120 kbytes 4096 bytes m37902fgmhp 248 kbytes 6144 bytes m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 4 203 50 ns (the fastest instruction at f(f sys ) = 20 mhz) 20 mhz (max.) 20 mhz (max.) (note) (note) 16 kbytes 8-bit ? 10 4-bit ? 1 16-bit ? 5 16-bit ? 3 (uart or clock synchronous serial i/o) ? 2 10-bit successive approximation method ? 1 (8 channels) 8-bit ? 3 12-bit ? 1 chip select area ? 4 (cs 0 cs 3 ). a bus cycle type and bus width can be set for each chip select area. 4 bits ? 2 channels; or 6 bits ? 1 channel + 2 bits ? 1 channel 5 external types, 13 internal types. each interrupt can be set to a priority level within the range of 0 7 by software. 1 external type, 3 internal types. built-in (externally connected to a ceramic resonator or quartz crystal resonator). the following multiplication methods are available: double, triple, and quadruple. 3.3 v0.3 v 39.6 mw (at f(f sys ) = 20 mhz, typ., pll frequency multiplier stopped) 3.3 v 5 ma up to 16 mbytes. note that bank ff 16 is a reserved area. 20 to 85 c cmos high-performance silicon gate process 100-pin plastic molded qfp functions (microcomputer mode) functions parameter number of basic machine instructions instruction execution time external clock input frequency f(x in ) system clock frequency f sys memory size programmable input/output ports multi-functional timers serial i/o a-d converter d-a converter watchdog timer chip-select wait control real-time output interrupts clock generating circuit pll frequency multiplier input/output withstand voltage output current flash memory (user rom area) ram flash memory (boot rom area) p0 p2, p4 p8, p10, p11 p3 ta0 ta4 tb0 tb2 uart0 and uart1 power supply voltage power dissipation ports input/output characteristics memory expansion operating ambient temperature range device structure package maskable interrups non-maskable interrups flash memory m37902fcmhp 120 kbytes (user rom area) m37902fgmhp 248 kbytes ram m37902fcmhp 4096 bytes m37902fgmhp 6144 bytes note: 5 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 3.3 v0.3 v 3.3 v0.3 v 3 modes: parallel i/o, serial i/o, and cpu reprogramming modes (note 1) 1 block (16 kbytes ? 1) (note 2) programmed per page (in a unit of 256 kbytes) user rom area + boot rom area user rom area user rom area total erase/block erase user rom area + boot rom area user rom area user rom area programming/erase control by software commands protected per block, by using a lock bit. 8 commands 100 functions (flash memory mode) functions parameter power supply voltage programming/erase voltage flash memory mode block division for erasure programming method erase method programming/erase control data protection method number of commands maximum number of reprograms user rom area boot rom area flash memory parallel i/o mode flash memory serial i/o mode flash memory cpu reprogramming mode flash memory parallel i/o mode flash memory serial i/o mode flash memory cpu reprogramming mode 2: on shipment, our reprogramming control firmware for the flash memory serial i/o mode has been stored into the boot rom area. note that the boot rom area can be erased/programmed only in the flash memory parallel i/o mode. user rom area m37902fcmhp 5 blocks (8 kbytes ? 3, 32 kbytes ? 1, 64 kbytes ? 1), total 120 kbytes m37902fgmhp 7 blocks (8 kbytes ? 3, 32 kbytes ? 1, 64 kbytes ? 3), total 248 kbytes notes 1: m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 6 vcc, vss md0 md1 reset x in x out byte v cont avcc, avss v ref p0 0 p0 7 p1 0 p1 7 p2 0 p2 7 p3 0 p3 3 p4 0 p4 7 power supply input md0 md1 reset input clock input clock output external data bus width select input filter circuit connection analog power supply input reference voltage input i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 input input input input output input input i/o i/o i/o i/o i/o apply 3.3 v0.3 v to vcc, and 0 v to vss. this pin controls the processor mode. connect this pin to v ss for the single-chip mode or memory expansion mode, and vcc for the microprocessor mode. connect this pin to vss. the microcomputer is reset when l level is applied to this pin. these are input and output pins of the internal clock generating circuit. connect a ceramic or quartz- crystal resonator between the x in and x out pins. when an external clock is used, the clock source should be connected to the x in pin, and the x out pin should be left open. this pin determines whether the external data bus has an 8-bit width or 16-bit width for the memory expansion mode or microprocessor mode. the width is 16 bits when l signal is input, and 8 bits when h signal is input. when byte = vss level, by the register setting, the external data bus for each of areas cs 1 to cs 3 can have a width of 8 bits. when using the pll frequency multiplier, connect this pin to the filter circuit. when not using, this pin should be left open. power supply input pins for the a-d converter and the d-a converter. connect avcc to vcc, and avss to vss externally. this is the reference voltage input pin for the a-d converter and the d-a converter. in single-chip mode port p0 is an 8-bit i/o port. this port has an i/o direction register, and each pin can be programmed for input or output. these pins enter the input mode at reset. in memory expansion and microprocessor modes address (a 16 a 23 ) is output. these pins also function as i/o port pins according to the register setting. in single-chip mode these pins have the same functions as port p0. in memory expansion and microprocessor modes the low-order 8 bits of data (d 0 d 7 ) are input/output. when the external data bus has an 8-bit width, address (la 0 la 7 ) output and data (d 0 d 7 ) input/output can be performed with the time-sharing method, according to the register setting. in single-chip mode or when 8-bit external data bus is used in memory expansion mode and microprocessor mode these pins have the same functions as port p0. when the 16-bit external data bus is used in memory expansion or microproce- ssor mode the high-order 8 bits of data (d 8 d 15 ) are input or output. in single-chip mode these pins have the same functions as port p0. in memory expansion mode p3 0 functions as an i/o port pin; and p3 1 , p3 2 , and p3 3 function as the output pins of rd, blw, bhw, respectively. p3 0 also functions as an output pin of rdy according to the register setting. when the external data bus has a width of 8 bits, the bhw pin functions as an i/o port pin (p3 3 ). in microprocessor mode p3 0 functions as an input pin of rdy; and p3 1 ,p3 2 , p3 3 function as the output pins of rd, blw, bhw, respectively. p3 0 also functions as an i/o port pin accord- ing to the register setting. when the external data bus has a width of 8 bits, the bhw pin functions as an i/o port pin (p3 3 ). in single-chip mode these pins have the same functions as port p0. in memory expansion mode p4 0 p4 7 function as i/o port pins. according to the register setting, these pins function as output pins or input pins of ale, 1 , hlda, hold, cs 0 cs 3 , respec- tively. in microprocessor mode p4 0 p4 4 function as output or input pins of ale, 1 , hlda, hold, cs 0 , and p4 5 p4 7 as i/o port pins, respectively. according to the register setting, p4 0 p4 3 also function as i/o port pins, and p4 5 p4 7 as output pins of cs 1 cs 3 . pin description (microcomputer mode) functions input/ output name pin 7 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers i/o i/o i/o i/o i/o i/o input functions input/ output name pin p5 0 p5 7 p6 0 p6 7 p7 0 p7 7 p8 0 p8 7 p10 0 p10 7 p11 0 p11 7 nmi in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for timers a0 a3, output pins for the real-time output, and input pins for the key-input interrupt. in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for timer a4, input pins for external interrupt inputs int 0 int 2 , and input pins for timers b0 b2. in addition to having the same functions as port p0 in the single-chip mode, these pins also function as input pins for the a-d converter, output pins for the d-a converter, and input pins for int 2 , int 3 , and int 4 . in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for uart0, uart1, output pins for d-a converter, and input pins for int 3 and int 4 . in single-chip mode these pins have the same functions as port p0. in memory expansion and microprocessor modes address (a 0 a 7 ) is output. in single-chip mode these pins have the same functions as port p0. in memory expansion and microprocessor modes address (a 8 a 15 ) is output. also, these pins function as i/o port pins according to the register setting. this pin is for a non-maskable interrupt. i/o port p5 i/o port p6 i/o port p7 i/o port p8 i/o port p10 i/o port p11 non-maskable interrupt m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 8 pin description (flash memory serial i/o mode) v cc , v ss md0 md1 _____ reset x in x out byte v cont avcc, avss v ref p0 0 p0 7 p1 0 p1 7 p2 0 p2 7 p3 0 p3 3 p4 0, p4 4 p4 7 p4 1 p4 2 p4 3 p5 0 p5 7 p6 0 p6 7 p7 0 p7 7 p8 0 p8 7 p10 0 p10 7 p11 0 p11 7 nmi pin power supply input md0 md1 reset input clock input clock output byte filter circuit connection analog supply input reference voltage input input port p0 input port p1 input port p2 input port p3 input port p4 sclk input sda i/o busy output input port p5 input port p6 input port p7 input port p8 input port p10 input port p11 non-maskable interrupt name input input input input output input input input input input input input input i/o output input input input input input input input input /output functions apply 3.3 v 0.3 v to vcc, and 0 v to vss. connect this pin to vss. connect this pin to vss via a resistor of 10 k ? to 100 k ? . the reset input pin. connect a ceramic resonator between the x in and x out pins, or input an external clock from the x in pin with the x out pin left open. connect this pin to vcc or vss. (this is not used in the flash memory serial i/o mode.) connect this pin to the filter circuit, or leave this pin open. (this is not used in the flash memory serial i/o mode.) connect avcc to vcc, and avss to vss. input an arbitrary level within the range of v ss v cc .(this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) i nput h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) this is an input pin for a serial clock. this is an i/o pin for serial data. connect this pin to v cc via a resistor (about 1 k ? ). this is an output pin for the busy signal. input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h , or leave this pin open. 9 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers basic function blocks these microcomputers have the same functions as the m37902fcchp. therefore, refer to the datasheet of the m37902fcchp. memory figures 1 and 2 show the memory maps. the address space is 16 mbytes from address 0 16 to ffffff 16 . the address space is di- vided into 64-kbyte units called banks. the banks are numbered from 0 16 to ff 16 . bank ff 16 is a reserved area for the development support tool. therefore, do not use bank ff 16 . internal flash memory and internal ram are assigned as shown in figures 1 and 2. addresses ffc0 16 to ffff 16 contain the reset and the interrupt vector addresses, and the interrupt vectors are stored there. for details, refer to the section on interrupts. assigned to addresses 0 16 to ff 16 are peripheral devices such as i/o ports, a-d converter, d-a converter, uart, timers, interrupt con- trol registers, etc. figures 7 and 8 show the location of sfrs. for the flash memory in the boot rom area, refer to the section on the flash memory mode. fig. 1 memory map of m37902fcmhp (single-chip mode) int 4 a-d conversion reserved area reserved area address matching detect reserved area reserved area reserved area reserved area reserved area uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 interrupt vector table timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brk instruction zero divide int 3 int 2 int 1 int 0 nmi reset dbc 000000 16 bank 0 16 ffffff 16 fe0000 16 00ffff 16 010000 16 01ffff 16 bank fe 16 000000 16 000800 16 0000ff 16 00fffe 16 00ffc0 16 internal ram 4096 bytes internal flash memory 120 kbytes (user rom area) peripheral devices control registers 001fff 16 002000 16 feffff 16 ff0000 16 0017ff 16 001800 16 00ffff 16 00ffc0 16 bank 1 16 bank ff 16 reserved area for development support tool m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 10 fig. 2 memory map of m37902fgmhp (single-chip mode) int 4 a-d conversion reserved area reserved area address matching detect reserved area reserved area reserved area reserved area reserved area uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 interrupt vector table timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brk instruction zero divide int 3 int 2 int 1 int 0 nmi reset dbc 000000 16 bank 0 16 ffffff 16 fe0000 16 00ffff 16 010000 16 01ffff 16 bank fe 16 000000 16 000800 16 0000ff 16 00fffe 16 00ffc0 16 internal ram 6144 bytes internal flash memory 248 kbytes (user rom area) peripheral devices control registers 001fff 16 002000 16 feffff 16 ff0000 16 00ffff 16 00ffc0 16 bank 1 16 bank ff 16 020000 16 02ffff 16 bank 2 16 030000 16 03ffff 16 bank 3 16 reserved area for development support tool 11 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig. 7 location of sfrs (1) 000000 16 000001 16 000002 16 000003 16 000004 16 000005 16 000006 16 000007 16 000008 16 000009 16 00000a 16 00000b 16 00000c 16 00000d 16 00000e 16 00000f 16 000010 16 000011 16 000012 16 000013 16 000014 16 000015 16 000016 16 000017 16 000018 16 000019 16 00001a 16 00001b 16 00001c 16 00001d 16 00001e 16 00001f 16 000020 16 000021 16 000022 16 000023 16 000024 16 000025 16 000026 16 000027 16 000028 16 000029 16 00002a 16 00002b 16 00002c 16 00002d 16 00002e 16 00002f 16 000030 16 000031 16 000032 16 000033 16 000034 16 000035 16 000036 16 000037 16 000038 16 000039 16 00003a 16 00003b 16 00003c 16 00003d 16 00003e 16 00003f 16 port p2 register port p3 register port p1 direction register port p0 direction register port p1 register port p0 register port p2 direction register port p3 direction register port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p8 direction register port p10 register port p11 register port p10 direction register port p11 direction register a-d control register 0 a-d control register 1 a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 a-d register 5 a-d register 6 a-d register 7 uart0 transmit/receive mode register uart0 baud rate register (brg0) uart0 transmit buffer register uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register (brg1) uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 uart1 receive buffer register address (hexadecimal notation) 000040 16 000041 16 000042 16 000043 16 000044 16 000045 16 000046 16 000047 16 000048 16 000049 16 00004a 16 00004b 16 00004c 16 00004d 16 00004e 16 00004f 16 000050 16 000051 16 000052 16 000053 16 000054 16 000055 16 000056 16 000057 16 000058 16 000059 16 00005a 16 00005b 16 00005c 16 00005d 16 00005e 16 00005f 16 000060 16 000061 16 000062 16 000063 16 000064 16 000065 16 000066 16 000067 16 000068 16 000069 16 00006a 16 00006b 16 00006c 16 00006d 16 00006e 16 00006f 16 000070 16 000071 16 000072 16 000073 16 000074 16 000075 16 000076 16 000077 16 000078 16 000079 16 00007a 16 00007b 16 00007c 16 00007d 16 00007e 16 00007f 16 address (hexadecimal notation) count start register one-shot start register timer a clock division select register timer a0 register timer a1 register timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register timer b2 register timer a1 mode register timer a0 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 1 watchdog timer register particular function select register 0 particular function select register 1 debug control register 0 int 3 interrupt control register uart0 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b2 interrupt control register int 1 interrupt control register watchdog timer frequency select register debug control register 1 int 4 interrupt control register uart1 transmit interrupt control register timer a2 interrupt control register timer b1 interrupt control register int 2 interrupt control register address comparison register 0 address comparison register 1 particular function select register 2 reserved area (note) note: do not write to this address. uart0 transmit/receive control register 0 up-down register processor mode register 0 a-d conversion interrupt control register uart0 receive interrupt control register int 0 interrupt control register reserved area (note) reserved area (note) m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 12 fig. 8 location of sfrs (2) 0000c0 16 0000c1 16 0000c2 16 0000c3 16 0000c4 16 0000c5 16 0000c6 16 0000c7 16 0000c8 16 0000c9 16 0000ca 16 0000cb 16 0000cc 16 0000cd 16 0000ce 16 0000cf 16 0000d0 16 0000d1 16 0000d2 16 0000d3 16 0000d4 16 0000d5 16 0000d6 16 0000d7 16 0000d8 16 0000d9 16 0000da 16 0000db 16 0000dc 16 0000dd 16 0000de 16 0000df 16 0000e0 16 0000e1 16 0000e2 16 0000e3 16 0000e4 16 0000e5 16 0000e6 16 0000e7 16 0000e8 16 0000e9 16 0000ea 16 0000eb 16 0000ec 16 0000ed 16 0000ee 16 0000ef 16 0000f0 16 0000f1 16 0000f2 16 0000f3 16 0000f4 16 0000f5 16 0000f6 16 0000f7 16 0000f8 16 0000f9 16 0000fa 16 0000fb 16 0000fc 16 0000fd 16 0000fe 16 0000ff 16 0000a0 16 0000a1 16 0000a2 16 0000a3 16 0000a4 16 0000a5 16 0000a6 16 0000a7 16 0000a8 16 0000a9 16 0000aa 16 0000ab 16 0000ac 16 0000ad 16 0000ae 16 0000af 16 0000b0 16 0000b1 16 0000b2 16 0000b3 16 0000b4 16 0000b5 16 0000b6 16 0000b7 16 0000b8 16 0000b9 16 0000ba 16 0000bb 16 0000bc 16 0000bd 16 0000be 16 0000bf 16 real-time output control register pulse output data register 0 pulse output data register 1 serial i/o pin control register 000080 16 000081 16 000082 16 000083 16 000084 16 000085 16 000086 16 000087 16 000088 16 000089 16 00008a 16 00008b 16 00008c 16 00008d 16 00008e 16 00008f 16 000090 16 000091 16 000092 16 000093 16 000094 16 000095 16 000096 16 000097 16 000098 16 000099 16 00009a 16 00009b 16 00009c 16 00009d 16 00009e 16 00009f 16 address (hexadecimal notation) cs 0 control register l cs 0 control register h cs 1 control register l cs 1 control register h cs 2 control register l cs 2 control register h cs 3 control register l cs 3 control register h area cs 0 start address register area cs 1 start address register area cs 2 start address register area cs 3 start address register reserved area (note) reserved area (note) port function control register external interrupt input control register external interrupt input read-out register d-a control register d-a register 0 d-a register 1 d-a register 2 flash memory control register note: do not write to this address. clock control register reserved area (note) reserved area (note) reserved area (note) address (hexadecimal notation) reserved area (note) reserved area (note) 13 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers flash memory mode these microcomputers contain the dinor (divided bit line nor)- type flash memory; and single-power-supply reprogramming is avail- able to this. these microcomputers have the following three modes, enabling reading/programming/erasure for the flash memory: flash memory parallel i/o mode and flash memory serial i/o mode, where the flash memory is handled by using an external pro- grammer. cpu reprogramming mode, where the flash memory is handled by the central processing unit (cpu). for each modes, refer to the datasheet m37902fcchp. figures 9 and 10 shows the block configuration of the internal flash memory of each microcomputer. these microcomputers have the same functions as the m37902fcchp except for the following: (1) power supply voltage (3.3 v 0.3 v) (2) electrical characteristics therefore, for the flash memory mode except for the above, refer to the datasheet m37902fcchp. fig 9. m37902fcmhp: block configuration of internal flash memory 16 kbytes 001fff 16 boot rom area user rom area 32 kbytes 8 kbytes 8 kbytes 8 kbytes 01ffff 16 003fff 16 005fff 16 006000 16 007fff 16 00ffff 16 010000 16 008000 16 00ffff 16 001fff 16 002fff 16 003000 16 003fff 16 007fff 16 008000 16 004000 16 002000 16 004000 16 001000 16 002000 16 byte address word address 000000 16 003fff 16 000000 16 byte addresses word addresses 64 kbytes total 120 kbytes notes 1: in the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: the boot rom area can be reprogrammed only in the flash memory parallel i/o mode. when the boot rom area is read out by the cpu, these addresses are shifted to addresses 00c000 16 00ffff 16 (byte addresses). 3: the reserved area for the serial programmer is assigned to addresses ffb0 16 ffbf 16 (byte addresses). when the flash memory serial i/o mode is used, do not program to this area. m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 14 fig 10. m37902fgmhp: block configuration of internal flash memory notes 1: in the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: the boot rom area can be reprogrammed only in the flash memory parallel i/o mode. when the boot rom area is read out by the cpu, these addresses are shifted to addresses 00c000 16 00ffff 16 (byte addresses). 3: the reserved area for the serial programmer is assigned to addresses ffb0 16 ffbf 16 (byte addresses). when the flash memory serial i/o mode is used, do not program to this area. 16 kbytes 001fff 16 boot rom area user rom area 32 kbytes 8 kbytes 8 kbytes 8 kbytes 01ffff 16 003fff 16 005fff 16 006000 16 007fff 16 00ffff 16 010000 16 008000 16 00ffff 16 001fff 16 002fff 16 003000 16 003fff 16 007fff 16 008000 16 004000 16 002000 16 004000 16 001000 16 002000 16 byte address word address 000000 16 003fff 16 000000 16 byte addresses word addresses 64 kbytes total 248 kbytes 64 kbytes 64 kbytes 02ffff 16 020000 16 017fff 16 010000 16 03ffff 16 030000 16 01ffff 16 018000 16 15 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers ac electrical characteristics (v cc = 3.3 v ?0.3 v, ta = 0 to 60 ?, f(f sys ) = 20 mhz (note)) the limits of parameters other than the above are same as those in the microcomputer mode. note: f(f sys ) indicates the system clock (fsys) frequency. parameter page programming time block erase time erase all unlocked block time lock bit programming time limits unit min. typ. max. 8 50 50 ? n 8 120 600 600 ? n 120 ms ms ms ms n = number of blocks to be erased symbol parameter limits unit i cc1 i cc2 i cc3 i cc4 min. typ. max. v cc power source current (at read) v cc power source current (at write) v cc power source current (at programming) v cc power source current (at erasing) 19 40 40 48 48 dc electrical characteristics (v cc = 3.3 v ?0.3 v, ta = 0 to 60 ?, f(f sys ) = 20 mhz (note)) limits of v ih , v il , v oh , v ol , i ih , and i il for each pin are the same as those in the microcomputer mode. note: f(f sys ) indicates the system clock (fsys) frequency. ma ma ma ma m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 16 unit v v v v v v v v v v v v v v v v v v ma ma ma ma mhz mhz max. 3.6 vcc v cc vcc vcc vcc vcc vcc 0.2 v cc 0.2 v cc 0.2 v cc 0.16 v cc 0.22 v cc 0.16 v cc 0.16 v cc ?0 ? 10 5 20 20 parameter power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage x in , reset, byte, md0, md1 high-level input voltage p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 high-level input voltage p0 0 ?0 7 (when the port p0 input level select bit = ?? high-level input voltage p0 0 ?0 7 (when the port p0 input level select bit = ?? high-level input voltage d 0 ? 7 , d 8 ? 15 high-level input voltage rdy, hold, ta0 in ?a4 in , ta0 out ?a4 out , tb0 in ?b2 in , ki 0 ?i 3 , int 0 ?nt 4 , nmi, ad trg , cts 0 , cts 1 , clk 0 , clk 1 , rxd 0 , rxd 1 high-level input voltage sclk, sda (note 1) low-level input voltage x in , reset, byte, md0, md1 low-level input voltage p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 low-level input voltage p0 0 ?0 7 (when the port p0 input level select bit = ?? low-level input voltage p0 0 ?0 7 (when the port p0 input level select bit = ?? low-level input voltage d 0 ? 7 , d 8 ? 15 low-level input voltage rdy, hold, ta0 in ?a4 in , ta0 out ?a4 out , tb0 in ?b2 in , ki 0 ?i 3 , int 0 ?nt 4 , nmi, ad trg , cts 0 , cts 1 , clk 0 , clk 1 , rxd 0 , rxd 1 low-level input voltage sclk, sda (note 1) high-level peak output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 high-level average output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 low-level peak output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 low-level average output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 external clock input frequency (note 2) system clock frequency symbol v cc av cc v ss av ss v ih v ih v ih v ih v ih v ih v ih v ih v il v il v il v il v il v il i oh(peak) i oh(avg ) i ol(peak) i ol(avg) f(x in ) f(f sys ) parameter power source voltage analog power source voltage input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7, v ref , x in , reset, byte, md0, md1, nmi, v cont output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 , x out power dissipation operating ambient temperature storage temerature symbol v cc av cc v i v o p d t opr t stg absolute maximum ratings recommended operating conditions (vcc = 3.3 v, ta = ?0 to 85 ?, unless otherwise noted) notes 1: pins sclk and sda are used only in the flash memory serial i/o mode. 2: when using the pll frequency multiplier, be sure that f(f sys ) = 20 mhz or less. 3: average output current is the average value of an interval of 100 ms. 4: the sum of i ol(peak) for ports p0?2, p8, p10, and p11 must be 80 ma or less, the sum of i oh(peak) for ports p0?2, p8, p10, and p11 must be 80 ma or less, the sum of i ol(peak) for ports p3?7 must be 80 ma or less, the sum of i oh(peak) for ports p3?7 must be 80 ma or less. unit v v v v mw ? ? ratings ?.3 to 4.6 ?.3 to 4.6 ?.3 to v cc +0.3 ?.3 to v cc +0.3 400 ?0 to 85 ?0 to 150 limits min. 3.0 0.8 vcc 0.7 v cc 0.7 vcc 0.5 vcc 0.5 vcc 0.5 vcc 0.5 vcc 0 0 0 0 0 0 0 typ. 3.3 v cc 0 0 17 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers unit v v v v v v v v a f(f sys ) = 20 mhz. cpu operates. ta = 25 c when clock is stopped. ta = 85 c when clock is stopped. test conditions i oh = ? ma i oh = ? ma i ol = 1 ma i ol = 1 ma v i = 3.3 v v i = 0 v v i = 0 v, no pullup transistor v i = 0 v, pullup transistor used when clock is stoped. parameter high-level output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 high-level output voltage p3 1 ?3 3 low-level output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 low-level output voltage p3 1 ?3 3 hysteresis rdy, hold, ta0 in ?a4 in , ta0 out ?a4 out , tb0 in ?b2 in , ki 0 ?i 3 , int 0 ?nt 4 , nmi, ad trg , cts 0 , cts 1 , clk 0 , clk 1 , rxd 0 , rxd 1 hysteresis reset hysteresis x in high-level input current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 , x in , reset, byte, md0, md1, nmi low-level input current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 3 , p5 0 ?5 3 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 , x in , reset, byte, md0, md1 low-level input current p4 4 ?4 7 , p5 4 ?5 7 , nmi ram hold voltage power source current symbol v oh v oh v ol v ol v t+ vt v t+ vt v t+ vt i ih i il i il v ram i cc min. 2.5 2.6 0.08 limits typ. ?.36 12 max. 0.5 0.4 0.5 1 0.26 4 ? ? ?.54 24 1 20 output-only pins are open, and the other pins are con- nected to vss or vcc. an external square-waveform clock is input. (pin x out is open.) the pll frequency multiplier stops its operation. dc electrical characteristics (vcc = 3.3 v, vss = 0 v, ta = ?0 to 85 ?, f(f sys ) = 20 mhz (note) ) ?.20 2 0.3 0.05 a ma v ma a m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 18 resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage r ladder t conv v ref v ia v ref = v cc v ref = v cc v ref = v cc f(f sys ) 20 mhz max. a-d converter characteristics (v cc = av cc = 3.3 v ?0.3 v, v ss = av ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) unit parameter symbol test conditions limits min. 10-bit resolution mode 8-bit resolution mode 10-bit resolution mode 8-bit resolution mode 5 5.90 2.45 (note) 2.7 0 10 ?3 ?2 v cc v ref bits lsb lsb k ? s v v note: this is applied when a-d conversion freguency ( ad ) = f 1 . d-a converter characteristics (v cc = 3.3 v, v ss = av ss = 0 v, v ref = 3.3 v, t a = ?0 to 85 ?, unless otherwise noted) unit parameter symbol limits typ. min. max. test conditions resolution absolute accuracy set time output resistance reference power source input current t su r o i vref (note) 1 2.5 8 ?1.0 3 4 3.2 bits % s k ? ma note: the test conditions are as follows: ?one d-a converter is used. ?the d-a register value of the unused d-a converter is ?0 16 . ?the reference power source input current for the ladder resistance of the a-d converter is excluded. s reset input low-level pulse width t w(resetl) symbol parameter min. limits unit reset input reset input timing requirements (v cc = 3.3 v ?0.3 v, v ss = 0v, ta = ?0 to 85 ?, unless otherwise noted) 2 max. typ. reset input t w(resetl) 19 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers t c(ta) t w(tah) t w(tal) f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz peripheral device input/output timing (v cc = 3.3 v?.3 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 20 mhz unless otherwise noted) ? for limits depending on f(f sys ), their calculation formulas are shown below. also, the values at f(f sys ) = 20 mhz are shown in ( ). timer a input (up-down input and count input in event counter mode) t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in -up) symbol tai out input cycle time tai out input high-level pulse width tai out input low-level pulse width tai out input setup time tai out input hold time parameter limits min. 2000 1000 1000 400 400 max. ns ns ns ns ns unit timer a input (external trigger input in pulse width modulation mode) t w(tah) t w(tal) symbol tai in input high-level pulse width tai in input low-level pulse width parameter min. 80 80 limits max. ns ns unit limits symbol parameter min. max. unit 8 10 9 f(f sys ) (400) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width ns ns ns 80 80 timer a input (external trigger input in one-shot pulse mode) limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (800) (400) (400) t c(ta) t w(tah) t w(tal) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width ns ns ns timer a input (gating input in timer mode) note : the tai in input cycle time requires 4 or more cycles of a count source. the tai in input high-level pulse width and the tai in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 20 mhz. timer a input (count input in event counter mode) t c(ta) t w(tah) t w(tal) symbol tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width parameter min. 80 40 40 limits max. ns ns ns unit f(f sys ) 20 mhz m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 20 t c(ta) t su(ta jin -ta jout ) t su(ta jout -ta jin ) symbol parameter min. 800 200 200 limits max. ns ns ns unit timer a input (two-phase pulse input in event counter mode) tai in input cycle time taj in input setup time taj out input setup time tai in input tai out input (up-down input) tai out input (up-down input) tai in input (when count by falling) tai in input (when count by rising) taj in input taj out input test conditions ?v cc = 3.3 v 0.3 v, ta = ?0 to 85 c ?input timing voltage : v il = 0.53 v, v ih = 1.65 v ?up-down and count input in event counter mode ?two-phase pulse input in event counter mode ?gating input in timer mode ?count input in event counter mode ?external trigger input in one-shot pulse mode ?external trigger input in pulse width modulation mode tc (ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in -up) t su(taj in -taj out ) t su(taj in -taj out ) t su(taj out -taj in ) t su(taj out -taj in ) t c(ta) t su(up-t in ) 21 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) timer b input (count input in event counter mode) symbol tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edge count) tbi in input high-level pulse width (both edge count) tbi in input low-level pulse width (both edge count) parameter limits min. 80 40 40 160 80 80 max. ns ns ns ns ns ns unit limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (800) (400) (400) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse period measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 20 mhz. limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (800) (400) (400) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse width measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 20 mhz. t c(ad) t w(adl) symbol ad trg input cycle time (minimum allowable trigger) ad trg input low-level pulse width parameter min. 1000 125 limits max. ns ns unit a-d trigger input m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 22 t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-q) t su(d-c) t h(c-d) serial i/o symbol clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width t x d i output delay time t x d i hold time r x d i input setup time r x d i input hold time parameter limits min. 200 100 100 0 20 90 max. 80 ns ns ns ns ns ns ns unit t w(inh) t w(inl) symbol int i input/nmi input/kii input high-level pulse width int i input/nmi input/kii input low-level pulse width parameter min. 250 250 limits max. ns ns unit external interrupt (int i ) input, nmi input, key input interrupt (kii) input t c(tb) t w(tbh) t w(tbl) t c(ck) t w(ckh) t w(ckl) t h(c - q) t d(c - q) t su(d - c) t w(inh) t w(inl) t h(c - d) t c(ad) t w(adl) tbi in input inti input, ad trg input clki input txdi output rxdi input nmi input, kii input test conditions vcc = 3.3 v 0.3 v, ta = 20 to 85 c input timing voltage : v il = 0.53 v, v ih = 1.65 v output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf 23 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers t d( 1-hldal) t d(rdh-hldal) t d(bxwh-hldal) t pxz(hldal-rdz) t pxz(hldal-bxwz) t pxz(hldal-csiz) t pxz(hldal-alez) t pxz(hldal-az) t pzx(hldal-rdz) t pzx(hldal-bxwz) t pzx(hldal-csiz) t pzx(hldal-alez) t pzx(hldal-az) t su(rdy- 1) t su(hold- 1) t h( 1-rdy) t h( 1-hold) symbol rdy input setup time hold input setup time rdy input hold time hold input hold time parameter limits min. 40 40 0 0 max. ns ns ns ns unit switching characteristics (v cc = 3.3 v?.3 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 20 mhz, unless otherwise noted) symbol hlda output delay time hlda low-level output delay time after read hlda low-level output delay time after write floating start delay time floating start delay time floating start delay time floating start delay time floating start delay time floating release delay time floating release delay time floating release delay time floating release delay time floating release delay time parameter min. tc ?5 (note) tc ?5 (note) ?5 ?5 ?5 ?5 ?5 0 0 0 0 0 limits max. 20 10 10 10 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns unit note: tc = 1/f(f sys ). ready, hold timing timing requirements (v cc = 3.3 v?.3 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 20 mhz, unless otherwise noted) m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 24 1 rdy input t su (rdy- 1 ) rd, blw, bhw : wait inserted by software (the above is applied when bus cycle = 1 + 2 ) : wait inserted by ready function rdy input t h ( 1 -rdy) test conditions v cc = 3.3 v 0.3 v, ta= 20 to 85 c rdy input, hold input:v il = 0.53 v, v ih = 1.65 v hlda output : v ol = 0.8v, v oh = 2.0 v, c l = 50 pf 1 hold input t su (hold- 1) t d ( 1-hldal) t pxz (hldal-rdz) t pxz (hldal-bxwz) t pxz (hldal-csiz) t pxz (hldal-az) t h ( 1-hold) t d ( 1-hldal) t pzx (hldal-rdz) t pzx (hldal-bxwz) t pzx (hldal-csiz) t pzx (hldal-alez) t pzx (hldal-az) hi-z hi-z hi-z hi-z hi-z hold input hlda output rd blw bhw cs i a 0 a 23 output t d (rdh-hldal) t d (bxwh-hldal) t pxz (hldal-alez) ale 25 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers t c(in) t w(half) t w(h) t w(l) t r t f t a(a-d) t a(a-d) t a(csil-d) t a(rdl-d) t su(d-rdl) t h(rdh-d) t a(ba-d) t h(ba-d) t a(la-d) max. 0.55 tc (w h + w l ) tc-45 (w h + w l -0.5) tc-35 (w h + w l -0.5) tc-35 w l ? tc-30 w l ? tc-35 min. 50 0.45 tc 0.5 t c ?6 0.5 t c ?6 6 6 15 0 8 (w h + w l -0.5)tc-35 (note) external clock input cycle time external clock input pulse width with half input-volage external clock input high-level pulse width external clock input low-level pulse width external clock input rise time external clock input fall time address access time (the address output select bit = 0) address access time (the address output select bit = 1) chip select access time read access time read data setup time data input hold time after read address access time at burst rom access data hold time after address at burst rom access address access time (the multiplexed bus select bit = 1) 1 +1 1 +2 1 +3 2 +2 limits external bus timing for limits depending on f(f sys ), their calculation formulas are shown below. symbol parameter ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit external clock input t r t f t w(l) t w(h) t w(half) x in t c(in) test conditions vcc = 3.3 v 0.3 v, ta = 20 to 85 c input timing voltage : v il = 0.66 v, v ih = 2.64 v (t w(h), tw(l), tr, tf ) output timing voltage : 1.65 v ( tc(in), tw(half) ) bus cycle w h w l 1 1 1 2 1 2 3 2 bus cycle w h w l 2 +3 2 +4 3 +3 3 +4 2 2 3 3 3 4 3 4 tc = 1/f(f sys ). timing requirements (v cc = 3.3 v?.3 v, v ss = 0 v, t a = ?0 to 85 ?, f(x in ) = 20 mhz, unless otherwise noted) note: this is independent of the value of the address output select bit s contents. m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 26 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns bus cycle = 2 + 2 bus cycle = 3 + 3 , 3 + 4 t d( 1-rdl) t d( 1-rdh) t d( 1-bxwl) t d( 1-bxwh) t d( 1l-csil) t d( 1l-csih) t d( 1h-a) t d( 1l-a) t w(aleh) t d(a-alel) t w(rdl) t w(rdh) t d(rdh-bxwh) t d(a-rdh) t d(a-rdh) t h(rdh-a) t h(rdh-a) t d(rdh-alel) t d(alel-rdh) t d(csil-rdh) t d(csil-rdl) t h(rdh-csil) t d(rdh-d) t w(bxwl) t w(bxwh) t d(bxwh-rdh) t d(a-bxwh) t d(a-bxwh) t h(bxwh-a) t h(bxwh-a) t d(bxwh-alel) t d(alel-bxwh) t d(csil-bxwh) t d(csil-bxwl) t h(bxwh-csil) t d(d-bxwl) t h(bxwh-d) t pxz(bxwh-dz) parameter switching characteristics (v cc = 3.3 v?.3 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 20 mhz, unless otherwise noted) max. 0 0 0 0 0 10 25 16 20 20 0.5tc + 10 min. ?8 ?8 ?8 ?8 ?0 ?2 ? ?0 0.5tc-19 tc-20 1.5tc-20 tc-30 1.5tc-30 2tc-30 0.5tc-19 tc-20 1.5tc-20 w l ? tc-15 w h ? tc-15 tc-15 w h ? tc-30 (w h -0.5)tc-19 8 0.5tc-10 0.5tc-19 tc-15 (w h -0.5)tc-19 (w h + w l -0.5)tc-20 0.5tc-14 tc-15 w l ? tc-15 w h ? tc-15 tc-15 w h ? tc-30 (w h -0.5)tc-19 8 0.5tc-10 0.5tc-19 tc-15 (w h -0.5)tc-19 (w h + w l -0.5)tc-20 0.5tc-14 w l ? tc-20 0.5tc-10 read low-level output delay time read high-level output delay time write low-level output delay time write high-level output delay time chip select low-level output delay time chip select high-level output delay time address output delay time (the address output select bit = 0) address output delay time (the address output select bit = 1) ale pulse width ale completion delay time after address stabilization (when the address output select bit = 0) ale completion delay time after address stabilization (when the address output select bit = 1) read output pulse width read output high-level width (note 1) write disable valid time after read (note 2) address valid time before read (when the address output select bit = 0) address valid time before read (when the address output select bit = 1) address hold time after read (when the address output select bit = 0) (note 2) address hold time after read (when the address output select bit = 1) (note 2) ale completion delay time after read start read disable valid time after ale completion limits symbol unit bus cycle = 1 + 1 , 1 + 2 , 1 + 3 bus cycle = 2 + 2 bus cycle = 2 + 3 , 2 + 4 , 3 + 3 , 3 + 4 bus cycle = 1 + 1 , 1 + 2 , 1 + 3 bus cycle = 2 + 2 bus cycle = 2 + 3 , 2 + 4 , 3 + 3 , 3 + 4 bus cycle = 2 + 2 bus cycle = 2 + 3 , 2 + 4 , 3 + 3 , 3 + 4 notes 1: when the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.). 2: when accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycl e is inserted.) or by 2tc (ns: two recovery cycles are inserted.). 3: this parameter is extended by tc (ns) when both of the following conditions are satisfied: ?when accessing the area where the recovery cycle insertion is selected. ?when two recovery cycles are inserted. bus cycle = 1 + 1 , 1 + 2 , 1 + 3 bus cycle = 2 + 2 bus cycle = 2 + 3 , 2 + 4 , 3 + 3 , 3 + 4 chip select valid time before read chip select output valid time before read completion chip select hold time after read next write cycle data output delay time after read (note 2) write output pulse width write output high-level width (note 1) read disable valid time after write (note 2) address valid time before write (when the address output select bit = 0) address valid time before write (when the address output select bit = 1) address hold time after write (when the address output select bit = 0) (note 2) address hold time after write (when the address output select bit = 1) (note 2) ale completion delay time after write start write disable valid time after ale completion chip select valid time before write chip select output valid time before write completion chip select hold time after write data output valid time before write completion data hold time after write (note 3) floating start delay time after write (note 3) 27 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers t d(la-rdh) t d(la-alel) t h(alel-la) t pxz(rdh-laz) t d(la-bxwh) t pzx(rdh-dz) address valid time before read ale completion delay time after address stabilization address hold time after ale completion floating start delay time address valid time before write floating release delay time bus cycle = 2 + 2 bus cycle = 3 + 3 , 3 + 4 bus cycle = 2 + 2 bus cycle = 3 + 3 , 3 + 4 switching characteristics (v cc = 3.3 v?.3 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 20 mhz, unless otherwise noted) parameter max. 5 min. (w h -0.5)tc-19 (note) tc-20 (note) 1.5tc-20 (note) 0.5tc-19 tc-15 (w h -0.5)tc-19 (note) 0.5tc-19 (note) limits symbol ns ns ns ns ns ns ns ns unit note: this is independent of the address output select bit s contents. m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 28 bus cycle t h(rdh-d) t h(rdh-a) t w(rdl) t a(csil-d) t a(rdl-d) t a(a-d) t d(csil-rdl) t su(d-rdl) t w(aleh) t d(rdh-alel) t c t d(a-alel) t w(rdh) t d(rdh-d) t d( 1-rdl) t h(rdh-a) t d(a-rdh) t d(csil-rdh) t a(a-d) t d(a-alel) t d( 1h-a) t d( 1l-a) t d( 1l-csil) t d( 1l-csih) t d( 1-rdh) t h(rdh-csil) t d(rdh-bxwh) t d(a-rdh) cs i rd ale 1 f sys blw bhw 29 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers t h(bxwh-a) t d(csil-bxwl) t w(bxwl) t d(bxwh-alel) t d(d-bxwl) t h(bxwh-d) t pxz(bxwh-dz) bus cycle t d( 1-bxwl) t h(bxwh-a) t d(a-bxwh) t d(csil-bxwh) t c t d(a-alel) t w(aleh) t d( 1h-a) t d( 1l-csil) t d( 1l-csih) t d(bxwh-rdh) t d( 1-bxwh) t h(bxwh-csil) t d(a-alel) t w(bxwh) t d(a-bxwh) t d( 1l-a) cs i rd ale blw bhw 1 f sys m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 30 t d(a-rdh) bus cycle t d(csil-rdl) t d(a-alel) t h(rdh-d) t h(rdh-a) t w(rdl) t a(csil-d) t a(rdl-d) t a(a-d) t su(d-rdl) t w(aleh) t c t w(rdh) t d(rdh-d) t d(alel-rdh) t d( 1-rdl) t d( 1-rdh) t h(rdh-d) t a(la-d) t a(rdl-d) t d(la-rdh) t su(d-rdl) t pzx(rdh-dz) t d(la-alel) t h(alel-la) t pxz(rdh-laz) t h(rdh-a) t d(a-rdh) t d(csil-rdh) t a(a-d) address input data address t d( 1h-a) t d( 1l-csil) t d( 1l-csih) t d(rdh-bxwh) t h(rdh-csil) t d(a-alel) t d( 1l-a) cs i rd ale blw bhw f sys 1 note: valid only when area cs 2 is accessed with the external data bus width = 8 bits. 31 m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers t d(csil-bxwl) t h(bxwh-a) t d(a-bxwh) t w(aleh) t w(bxwl) t d(d-bxwl) t h(bxwh-d) t pxz(bxwh-dz) t d(a-alel) t w(bxwh) t d(alel-bxwh) bus cycle t d( 1-bxwl) t h(bxwh-d) t pxz(bxwh-dz) t d(d-bxwl) t h(alel-la) t d(la-alel) t d(la-bxwh) t c t h(bxwh-a) t d(a-bxwh) t d(csil-bxwh) address output data t d( 1-bxwh) t d( 1h-a) t d( 1l-csil) t d( 1l-csih) t d(a-alel) t h(bxwh-csil) t d(bxwh-rdh) t d( 1l-a) cs i rd ale blw bhw f sys 1 note: valid only when area cs 2 is accessed with the external data bus width = 8 bits. m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 32 t h(ba-d) t d(rdh-bxwh) blw bhw rd t a(rdl-d) t d(a-rdh) cs i t h(rdh-a) t a(csil-d) t a(a-d) t a(ba-d) t h(ba-d) t h(ba-d) t h(rdh-d) t a(ba-d) t a(ba-d) t h(rdh-csil) t d(csil-rdh) t d(a-alel) t w(aleh) ale t d(rdh-alel) t w(rdh) t d(a-rdh) t h(rdh-a) t a(a-d) burst rom access: bus cycle = 1 + 1 , 1 + 2 , 1 + 3 , 2 + 3 , 2 + 4 d 0 d 7 , d 8 d 15 test conditions v cc = 3.3 v 0.3 v, ta = 20 to 85 c input timing voltage : v il =0.53 v, v ih =1.65 v output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =15 pf (cs i ) output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =50 pf (except for cs i ) a 0 a 23 (when the address output select bit = 0) a 0 a 23 (when the address output select bit = 1) t d(a-alel) m37902fcmhp, m37902fgmhp single-chip 16-bit cmos microcomputer mitsubishi microcomputers package outline lqfp100-p-1414-0.50 weight(g) jedec code eiaj package code lead material cu alloy 100p6q-a plastic 100pin 14 ? 14mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 1.0 m d 14.4 m e 14.4 10 0 0.1 1.0 0.7 0.5 0.3 16.2 16.0 15.8 16.2 16.0 15.8 0.5 14.1 14.0 13.9 14.1 14.0 13.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e e c h e 1 76 75 51 50 26 25 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100 notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customer? application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party? rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommen ded that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibilit y for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. ?2000 mitsubishi electric corp. new publication, effective jun., 2000. specifications subject to change without notice. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. rev. rev. no. date 1.0 first edition 990305 2.0 refer to corrections and supplementary explanation for ?37902fxm datasheet (rev.a)? 990625 3.0 the following are revised/added points in this edition: 990917 ?page 20; recommended operating conditions corrections and supplement ar y explanation for m37902fxm dat asheet ( rev. b) no.1 page erro r correction (1/5) page 3 , b lo c k diagra m , no t e : note: r am 2048 bytes 4096 bytes 6144 bytes 6144 bytes 12288 bytes 12288 bytes m37902f8mhp m37902fcmhp m37902femhp m37902fgmhp M37902FHMHP m37902fjmhp flash memory 60 kbytes 120 kbytes 184 kbytes 248 kbytes 370 kbytes 498 kbytes note: ram 4096 bytes 6144 bytes m37902f c mhp m37902fgmhp flash memory 120 kbytes 248 kbytes pa ge 4 , ch ip-selec t wait control all pages, heade r preliminary notice: this is not a final specification. some parametric limits are subject to change. (deleted) p6 3 / int 2 p6 4 / int 2 page 2, pin configuration m37902f8mhp , m37902f c m h p, m37902f emhp, m37902fgmhp, m 37 902fhmhp , m37902fjmhp m37902f c m hp , m37902f g mhp [m 379 02f8mhp] fl ash memor y (user r o m ar ea ) .. .... .... ... .... .... .60 kbytes ra m ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... .... .2048 bytes (deleted) [m 379 02femhp ] fl ash memor y (user r o m ar ea ) .. .... .... ... .... ...184 kbytes ra m ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... .... .6144 bytes (deleted) [m 379 02fhmhp ] fl ash memor y (user r o m ar ea ) .. .... .... ... .... ...370 kbytes ra m ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... ...12288 byt e s (deleted) [m37902fjmhp] flash memory (user rom area) ....................498 kbytes ram...............................................................12288 bytes (deleted) page 1, disti n cti ve feat u res ; m emor y the fastest instruction at 26 mhz frequency .............38 ns the fastest instruction at 20 mhz frequency .............50 n s page 1, disti n cti ve feat u res ; instruction execution t i m e page 1, application c ontrol devices for personal computer peripheral equip- ment such as cd-rom drives, dvd-rom drives, hard disk drives, high density fdd, printers control devices for office equipment such as copiers and facsimiles control devices for industrial equipment such as commu- nication and measuring instruments c ontrol devices for personal computer peripheral equip- ment such as cd-rom drives, dvd-rom drives, hard disk drives, high density fdd, printers m37902f8mhp m37902fcmhp m37902femhp m37902fgmhp M37902FHMHP m37902fjmhp m37902f c mhp m37902fgmhp (type) (type) c hi p sel ect area ? 4 ( c s 0 c s 3 ) . a wai t number an d bus width can be set for each ch ip select ar ea. c hip select area ? 4 ( c s 0 c s 3 ). a bus cycle type and bus width can be set for each chip select area. pa ge 4 , i nstruction executio n time 38 ns (the fastest instruction at f(f sys ) = 26 mhz) 50 ns (the fastest instruction at f(f sys ) = 20 mhz) pa ge 4 , ext ern al clock inp ut frequency f(x in ), system clock f req uency f sys 26 m h z (max. ) 20 mhz (max.) corrections and supplement ar y explanation for m37902fxm dat asheet ( rev. b) no.2 page page 9, fig. 1 erro r correction (2/5) 00ff c0 16 internal f l ash memory 120 kbytes (user rom area) 00ffff 16 002000 16 00ffc0 16 internal f l ash memory 120 kbytes (user rom area) 00ffff 16 002000 16 pa ge 4 , operating temperatur e rang e page 6, p4 0 ?4 7 in microprocessor mode according to the register setting, p4 0 ?4 4 also in microprocessor mode according to the register setting, p4 0 ?4 3 also operating temperature rang e operating ambi ent temper at u re r ange pa ge 4 , powe r dissi pation 51.5 m w (at f( f sys ) = 26 mhz, t yp. , 39.6 mw (at f(f sys ) = 20 mhz, typ., page 4, no t e: note: ram 2048 bytes 4096 bytes 6144 bytes 6144 bytes 12288 bytes 12288 bytes m37902f8mh p m37902fc mhp m37902femh p m37902fgmhp m37902fh mhp m37902fjmh p flash memory (user rom area) 60 kbytes 120 kbytes 184 kbytes 248 kbytes 370 kbytes 498 kbytes m37902f8mh p m37902fcmhp m37902femhp m37902fgmhp M37902FHMHP m37902fjmhp note: ram 4096 bytes m37902f c mh p flash memory (user rom area) 120 kbytes m37902f c mh p m37902f g mh p m37902f g mh p 248 kbytes 6144 bytes page 5, n ot e s 1: user r o m area m37902f8mh p 4 blocks m37902fcmhp 5 blocks m37902femh p 6 blocks m37902fgmhp 7 blocks M37902FHMHP 9 blocks m37902fjmh p 11 blocks user r o m area m37902fc mhp 5 blocks m37902fgmhp 7 blocks fig. 2. memory map of m37902f c mhp (single-chip mode) fig. 1. memory map of m37902f c mhp (single-chip mode) mem ory m ap of m 379 02f8mhp (sing le- ch ip m ode) (deleted) mem ory m ap of m 379 02femhp (si ngle-chip mode) (deleted) mem ory m ap of m 379 02fhmhp (si ngle-chip m od e) (deleted) mem ory m ap of m 379 02fjmhp (singl e- chi p m ode) (deleted) corrections and supplement ar y explanation for m37902fxm dat asheet ( rev. b) no.3 page erro r correction (3/5) page 10, fig. 2 00ff c0 16 internal f l ash memory 248 kbytes (user rom area) 00 ffff 16 003800 16 00ffc0 16 internal flash memory 248 kbytes (user rom area) 00ffff 16 003800 16 page 11, fig. 7 port 011 direction re g ister 000019 16 00001a 16 port p11 direction re g ister 000019 16 00001a 16 000000 16 000001 16 000000 16 000001 16 reserved area ( note ) reserved area ( note ) address 00 16 , 01 16 address 19 16 fi g. 4. m emory map of m37902f g mhp (si ngle-chip mode) fi g. 2. m emory map of m37902f g mhp (si ngle-chip mode) page 12, fig. 8 serial i/o control r e g i st e r 0 000ac 16 0000ad 16 serial i/o p in control re g ister 0 000ac 16 0000ad 16 reserved area ( note ) 0000a6 16 0000a7 16 ( deleted ) address a6 16 address ac 16 , ad 16 m37902f8mhp : block configuration of i nter nal flash mem ory (deleted) fig. 10. m37902f c mhp : block configuration of internal flash memory fig. 9. m37902f c mhp : block configuration of inter- nal flash memory page 13, fig. 9 m37902femhp : block configuration of internal flash memory (deleted) fi g. 12. m 37 902f g m h p : bl ock co nf i gur ation of internal flash m e m ory fig. 10. m37902f g mhp : block configuration of inter- nal flash memory page 14, fig. 1 0 m37902fh m hp : block configu r ation of inter na l f l ash mem ory (deleted) m37902fjmhp : block configuration of i nt e r nal flash mem ory (deleted) corrections and supplement ar y explanation for m37902fxm dat asheet ( rev. b) no.4 page erro r correction (4/5) page 16, recommend ed ope r at ing c o n diti ons page 17, dc electrical characteristics ta = 25 c ta = 85 c a icc ta = 25 c 1 ta = 85 c a 20 icc page 16, ab solut e max im um ra tings 300 ratings s ymbol p d p ower di sspat i on p arameter unit mw 400 rating s s ymbol p d p ower di sspat i on p arameter uni t mw t opr o perating t em perature t opr o perating ambien t temperature page 1 5 dc electri cal c haracteristics; ac electri cal ch aract er istic s (vcc = 3.3 v 0.3 v, ta = 0 to 60 c , f(fsys) = 26 mhz (note)) (vcc = 3.3 v 0.3 v, ta = 0 to 60 c , f(fsys) = 20 mhz (note)) 2: , be sure that f (f sys ) = 26 m hz or less. 2: , be sure that f (f sys ) = 20 m hz or less. 26 lim its s ymbol f (x in ) ext e rnal clcok input f r equency (n o te 2) p arameter f ( sys ) s yst e m cl cok f requen cy typ. min. max. 26 20 limits s ymbol f (x in ) ext e rnal clcok input f r equency (n o te 2) p arameter f ( f sys ) s yst e m cl cok f requen cy typ. mi n. max. 20 min. 31.2 limits max. typ. s ymbol i cc 15.6 f ( f sys ) = 26mhz, cpu oper at es. test condi t i ons (vcc = 3.3 v, vss = 0 v , f(f sys ) = 26 mhz ( n ote ) ) (vcc = 3.3 v, vss = 0 v , f(f sys ) = 20 mhz ( n ote ) ) min. 24 lim its max. typ. s ymbol i cc 12 f ( f sys ) = 20mhz, cpu oper at es. test conditions min. 1.89 (note) limits max. s ymbol t c o n v 4.54 f(f sys ) 26mhz test conditions mi n. 2.45 (note) lim its max. s ymbol t conv 5.90 f ( f sys ) 20mhz test conditions page 18, a - d c o n ve rte r ch ara cte ristics; the mini um val ue of t c o n v page 1 9 peripheral device input/outpu t timing (vcc = 3.3 v 0.3 v , f(f sys ) = 26 mhz, unless othr e- wi se noted) ? a t f ( f sys ) = 2 6 m h z a r e s h o w n i n ( ) . (vcc = 3.3 v 0.3 v , f(f sys ) = 20 mhz, unless othr e- wi se noted) ? ?at f (f sys ) = 20 mhz are shown in ( ). corrections and supplement ar y explanation for m37902fxm dat asheet ( rev. b) no.5 page erro r correction (5/5) page 19, t im e r a inpu t ; (gating input in t i mer mode) mi n. f ( f sys ) limits max. s ymbol t c(ta ) 16 ? 10 f ( f sys ) 26mh z p arameter 9 (615) f ( f sys ) t w (tah ) 8 ? 10 f ( f sys ) 26mh z 9 (307) f ( f sys ) t w (tal) 8 ? 10 f ( f sys ) 26mh z 9 (307) no t e: the co unt source = f 2 at f(f sys ) 2 6 mhz. page 19, t im e r a inpu t ; (ext erna l t ri gge r inpu t in one-sho t pul se mode) t c(ta) page 21, t im e r b inpu t ; (pul se per iod measurement mode), (pulse w idth me asure- ment mode) t c(tb) f ( f sys ) 26mh z t w (tbh ) f ( f sys ) 26mhz t w (tbl) f ( f sys ) 26mhz note: the count source = f 2 at f(f sys ) 26 mhz. page 23, ready, hold timing; timing requirements, switching characteristic s (vcc = 3.3 v 0.3 v , f(f sys ) = 26 mhz, unless othr e- wi se noted) pag es 25,26,27 , external bus timi ng; (tim ing r equireme nt s), (swi t ch ing char act eri st i cs) min. f ( f sys ) limits max. s ymbol t c(ta ) 16 ? 10 f ( f sys ) 20mh z p arameter 9 (800) f ( f sys ) t w (tah ) 8 ? 10 f ( f sys ) 20mh z 9 (400) f ( f sys ) t w (tal) 8 ? 10 f ( f sys ) 20mh z 9 (400) no t e: the co unt source = f 2 at f(f sys ) 2 0 mhz. mi n. limits max. s ymbol p arameter f ( f sys ) 8 ? 10 f ( f sys ) 26mh z 9 (307) t c(ta) mi n. lim its max. s ymbol p arameter f ( f sys ) 8 ? 10 f ( f sys ) 20mh z 9 (400) min. limits max. s ymbol p arameter f ( f sys ) 16 ? 10 9 (615) f ( f sys ) 8 ? 10 9 (307) f ( f sys ) 8 ? 10 9 (307) t c(tb) f ( f sys ) 20mh z t w (tbh ) f ( f sys ) 20mhz t w (tbl) f ( f sys ) 20mhz min. limits max. s ymbol p arameter f ( f sys ) 16 ? 10 9 (800) f ( f sys ) 8 ? 10 9 (400) f ( f sys ) 8 ? 10 9 (400) note: the count source = f 2 at f(f sys ) 20 mhz. (vcc = 3.3 v 0.3 v, f(f sys ) = 20 mhz, unless othre- wise noted) page 26, external bu s timing; (timin g requirements ) t c(in) external clock 38 mi n. limits max. s ymbol p arameter t c(in) external clock 50 mi n. lim its max. s ymbol p arameter |
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